Dr. Ja-beom "JB" Koo, earned his B.S. and M.S. degrees in 2006 and 2008 respectively from Korea University in South Korea. After graduation, he worked at SK Hynix Semiconductor Inc. in Korea until August 2011, as an Analog Circuit Design Engineer. There, he focused on designing High-speed input/output (I/O) circuit for 512GB Graphic Dynamic Random Access Memory (DRAM) memory chip with 45nm CMOS technology.
Dr. Koo received his Ph.D. degree in Electrical Engineering from the University of Washington, Seattle, in March 2016. He then joined the Analog I/O design team at Intel Corporation in Hillsboro, OR for i5/i7 CPU design. After the first tape-in with CMOS 10nm technology, he moved to the RF technology team in Advanced Design group. He worked as a RF/Analog Circuit Design Engineer and participating in 140GHz Transceiver/Receiver system design for server chips communication. He also had additional responsibilities as a lab manager controlling all measurements for Intel 22nm FinFet technology development. His current research interests are in the area of RF IC design for wireless applications.